Controlled Collapse Chip Collection (C4) is a technology where a semiconductor chip is interconnected to its package by an array of solder balls on the top or face of the chip. C4 offers a high input/output density by positioning solder balls anywhere on the face of the chip. In addition, interconnection by very small solder balls lowers inductance, thereby enhancing overall electrical performance. Finally, C4 allows for lower process complexity due to the relaxation of pitch separation requirements between balls and the self-aligning property of C4 chip attach.
Briefly, the Controlled Collapse Chip Connection (C4) process comprises forming the desired number of input/output pads on both the chip and package in alignment, forming a Ball Limiting Metallurgy (BLM) at the pads of the chip followed by depositing solder balls on the BLM. To connect the chip to the package, the balls are aligned with their corresponding pads on the package and the chips and the package are heated to a temperature sufficient to melt and reflow the solder into balls to connect the pads on the package. Upon cooling, the input/output pads of the chips and package are physically connected. At the input/output pads, the BLM contains the flow of the solder in the solder balls while the balls are in their melted and reflow state.
From the inception of the C4 technology, the solder composition consisted of a combination of lead (Pb) and tin (Sn), normally with the Pb being the larger percentage to enable the proper reflow characteristics, while the Ball Limiting Metallurgy (BLM) contained no lead (Pb). Normally in the past, a high melt composition of, for example, 97/3 Pb/Sn was used. Because of the health hazard to humans by Pb, the use of Pb solder has been replaced by Pb-free solder in the electronics industry, including the C4 technology. However, it has been found that Pb-free solder creates undesirable stresses in the chip during chip joining and subsequent thermal processing to reflow the solder, stresses which were not present with the 97/3 Pb/Sn composition. These stresses, which occur at the Back End of the Line (BEOL), can initiate fracture below the BLM connection pad at points which appear in the form of discrete white spots when viewed using acoustic microscopy. For an organic package laminate configuration on which the chip is mounted, these stresses can be catastrophic, resulting in delaminating or breakage of structural elements located directly below the interconnect during processing at the BEOL. This situation is worse for “fine pitch” C4 technologies when the C4 density increases with a higher number of I/Os. A typical C4/BLM chip interconnect structure comprises, herein, an aluminum landing pad accessed through a via opening in a final insulating material, such as polyimide or a polyimide/silicon oxide/silicon nitride composite. The C4/BLM lies directly over this aluminum metal pad, which is positioned over and in a via structure in a hard insulating layer of herein silicon oxide/silicon nitride. The stresses, which includes a vertical tensile stress, are intrinsically related to thermal coefficient (TCE) mismatch between the chip and package laminate and are translated through the mechanically stiff or brittle Pb-free solder to the chip through this vertical interconnect, creating a separation of layers at the BEOL. These separations ultimately result in electrical opens either during reliability testing or by failure while operating in the field. The stresses causing these separations are at their highest where the final dielectric via edge contacts the metal pad, herein aluminum, in that the via edge acts to focus the stress effect locally. The stress is proportional to the via wall thickness or via height, but is generally reduced over the bulk insulating layer, herein polyimide, as a direct function of the thickness of the insulating layer.